assign x = condition_a ? foo :
condition_b ? bar :
condition_c ? baz :
condition_d ? qux :
quux;
conds_onehot: assert property ($onehot0({condition_a, condition_b, condition_c, condition_d, condition_e}));
assign x = ({8{condition_a}} & foo)
| ({8{condition_b}} & bar)
| ({8{condition_c}} & baz)
| ({8{condition_d}} & qux)
| ({8{condition_e}} & quux);{8{foo}} is Verilog for repeat foo 8x)