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pathetic piss kitten @kitten@elizabeth.cat
1mo
my archenemy, nested ternary operators
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erincandescent 💜 @erincandescent@erincandescent.net
1mo
@kitten you would hate your average (System)Verilog file, its practically standard to write things like
assign x = condition_a ? foo :
           condition_b ? bar :
           condition_c ? baz :
           condition_d ? qux :
                         quux;
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pathetic piss kitten @kitten@elizabeth.cat
1mo
@erincandescent nooooo neocat_cry

although at least this is a serially nested ternary. the one I saw had subternaries in both branches of the main ternary
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erincandescent 💜 @erincandescent@erincandescent.net
1mo
@kitten it's also pretty common to see "opencoded" conditions e.g. when you can assume due to structural factors that only one condition will ever be true:
conds_onehot: assert property ($onehot0({condition_a, condition_b, condition_c, condition_d, condition_e}));

assign x = ({8{condition_a}} & foo)
         | ({8{condition_b}} & bar)
         | ({8{condition_c}} & baz)
         | ({8{condition_d}} & qux)
         | ({8{condition_e}} & quux);



HDL is a weird world!
:neocat_think:1
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erincandescent 💜 @erincandescent@erincandescent.net
1mo
@kitten ({8{foo}} is Verilog for repeat foo 8x)
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pathetic piss kitten @kitten@elizabeth.cat
1mo
@erincandescent .......why do they do that?
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erincandescent 💜 @erincandescent@erincandescent.net
1mo
@kitten produces smaller and hence faster synthesis outputs (assuming that the synthesis tool couldn't prove the mutual exclusiveness of the conditions in the original, which it probably can't. They can be pretty dumb)
:neocat_think:1
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